The increase in the number of semiconductor elements on wiring substrates has resulted in a demand for wiring substrates with reduced thickness and an increased number of wiring patterns. To meet such demands, a coreless wiring substrate has been developed. The coreless wiring substrate does not include a core substrate (support member) which has high rigidity and is thicker than an interlayer insulation layer. Japanese Laid-Open Patent Publication No. 2011-124555 describes such a coreless wiring substrate.
A basic method for manufacturing a coreless wiring substrate will now be described. A provisional substrate is first prepared as a support substrate. Then, a wiring pattern including pads is formed on the provisional substrate. A given number of build-up wiring layers and insulations layers are stacked on the provisional substrate. Finally, the provisional substrate is removed.
In a wiring substrate that is manufactured through the method described above, the wiring patterns that include pads are formed on the same plane as the outermost insulation layer. In other words, the upper surface of each wiring pattern is flush with (i.e., located on the same level as) the upper surface of the outermost insulation layer. In such a wiring substrate, the wiring patterns easily delaminate from the insulation layer.